Optimizing compilation for data cache memories is made difficult by (1) the need to statically analyze the program behavior, (2) the complexity of cache hierarchies and policies, and (3) the intricate interplay with a superscalar microarchitecture. Analytical cache modeling typically focuses on the first two challenges, approximating away instruction scheduling and speculation (including data prefetching). While much progress has been made on such models, their practical usage remains very limited. We address this specific gap between analysis accuracy and effective performance. We analyze how effective cache models can be to select profitable optimizations, and study the sensitivity of these optimizations to cache modeling accuracy. We study a representative range of tensor algebra applications, where all kernels have already been systematically vectorized and optimized for instruction-level parallelism at the register level. We consider four cache models including two analytical ones: (i) a state-of the-art fully-associative analytical model; (ii) a novel approximate set associative analytical cache model; (iii) a state-of-the-art cache simulator; and (iv) direct measurement of hardware counters. We show that, while fully associative models are currently the only scalable ones available to compiler passes, they are not well correlated with performance. On the contrary, supporting some level of set associativity yields much better results, on par with the most accurate (dynamic) simulated and measured cache misses.