Almost Scalable Pipeline Flush
Résumé
Modern high-performance general purpose processors rely on an instruction window from which instructions are executed in a dataflow manner. Instruction window scaling is notably tied to register renaming. Indeed, on a pipeline flush some designs repair the Rename Map Table (RMT, maps architectural to physical registers) by iteratively undoing flushed mappings. This incurs a latency penalty that grows linearly with the instruction window size. To address this, modern designs use RMT checkpoints, which makes the latency of restoring the RMT state constant. However, RMT checkpoints increase the delay and power consumption of the renaming process, and can cause correct path instructions to be thrown away. In this paper, we revisit the algorithms used to restore the RMT state and propose an alternative to full-fledged checkpointing that provides comparable performance using a single checkpoint.
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