Almost Scalable Pipeline Flush - Techniques of Informatics and Microelectronics for integrated systems Architecture
Communication Dans Un Congrès Année : 2024

Almost Scalable Pipeline Flush

Arthur Perais
Trevor E Carlson
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Résumé

Modern high-performance general purpose processors rely on an instruction window from which instructions are executed in a dataflow manner. Instruction window scaling is notably tied to register renaming. Indeed, on a pipeline flush some designs repair the Rename Map Table (RMT, maps architectural to physical registers) by iteratively undoing flushed mappings. This incurs a latency penalty that grows linearly with the instruction window size. To address this, modern designs use RMT checkpoints, which makes the latency of restoring the RMT state constant. However, RMT checkpoints increase the delay and power consumption of the renaming process, and can cause correct path instructions to be thrown away. In this paper, we revisit the algorithms used to restore the RMT state and propose an alternative to full-fledged checkpointing that provides comparable performance using a single checkpoint.
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Dates et versions

hal-04766948 , version 1 (05-11-2024)

Identifiants

  • HAL Id : hal-04766948 , version 1

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Arthur Perais, Trevor E Carlson. Almost Scalable Pipeline Flush. Conférence francophone d'informatique en Parallélisme, Architecture et Système (COMPAS 2024), Jul 2024, Nantes, France. ⟨hal-04766948⟩

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