Back-side-illuminated 1.4um pixel with a vertically pinned photodiode based on hole collection, PMOS readout chain and active side-wall passivation - CNRS - Centre national de la recherche scientifique Accéder directement au contenu
Communication Dans Un Congrès Année : 2015

Back-side-illuminated 1.4um pixel with a vertically pinned photodiode based on hole collection, PMOS readout chain and active side-wall passivation

Résumé

To further improve the characteristics of CMOS image sensors (CIS), we propose a back-side illuminated pixel integrating a vertically pinned and P-type photodiode (which collects holes) and PMOS readout circuitry. It has been designed in a 1.4 mu m-pitch, a two-transistor (2T) shared readout architecture and fabricated in a combined 65nm and 90nm technology. The vertically pinned photodiode takes up almost the entire volume of the pixel, allowing a full well capacity (FWC) exceeding 7000h(+). With a conversion factor around 120 mu V/h(+), the output swing approaching 1V is achieved on the column voltage. The pixel also integrates capacitive deep trench isolation (CDTI) to tackle electrical and optical crosstalk issues. The effective passivation of trench interface by CDTI bias control is demonstrated for a hole-based pixel. As expected, PMOS transistors have much lower trapping noise compared to NMOS counterparts. The PMOS source follower has an average temporal noise of 195 mu V, mainly dominated by thermal noise contribution.
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Dates et versions

hal-01489321 , version 1 (14-03-2017)

Identifiants

  • HAL Id : hal-01489321 , version 1

Citer

Bastien Mamdy, F. Roy, Nayera Ahmed, Guo-Neng Lu. Back-side-illuminated 1.4um pixel with a vertically pinned photodiode based on hole collection, PMOS readout chain and active side-wall passivation. Annual Conference of the Chinese-Society-for-Optical-Engineering on Applied Optics and Photonics, China (AOPC),, 2015, Beijing, China. ⟨hal-01489321⟩
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