Technology-agnostic power optimization for AES block cipher - CNRS - Centre national de la recherche scientifique Access content directly
Conference Papers Year :

Technology-agnostic power optimization for AES block cipher

Kais Chibani
  • Function : Author
Adrien Facon
  • Function : Author
Sylvain Guilley
Youssef Souissi
  • Function : Author
  • PersonId : 971834


On the one hand, IoT applications require low-power consumption. On the other hand, they also need to embed strong cryptographic algorithms to protect the data they manipulate. We address this issue in the context of the AES block cipher. The challenge is to design an AES module consuming as little as possible, mostly by leveraging on the architecture. This paper presents two contributions. First of all, we present design guidelines for low-power AES, including lazy dataflow, glitch reduction techniques in combinational logic and algebraic simplification of diffusion operations. These optimizations allow to divide by two the power consumption of the AES module. Second , we show a methodology to improve the power consumption using a high-level technology-independent power and security evaluation tool (Virtualyzr).
Fichier principal
Vignette du fichier
ICECS_AES_Optimization.pdf (290.97 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-02915635 , version 1 (14-08-2020)



Kais Chibani, Adrien Facon, Sylvain Guilley, Youssef Souissi. Technology-agnostic power optimization for AES block cipher. ICECS, Dec 2018, Bordeaux, France. pp.397-400, ⟨10.1109/ICECS.2018.8617921⟩. ⟨hal-02915635⟩
35 View
110 Download



Gmail Facebook Twitter LinkedIn More