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Communication Dans Un Congrès Année : 2021

A gm/ID Design Methodology for 28 nm FD-SOI CMOS Resistive Feedback LNAs

Résumé

This paper presents a simple and efficient methodology for Resistive Feedback LNAs (RF-LNAs) design which uses the inversion level of the transistor as a design parameter in order to optimize the energy efficiency. The method uses a simple 4 parameter-based model valid in all regions of operation and allows a preliminary sizing based on an analytical study. A practical design in a 28 nm FD-SOI technology shows that this methodology is well suited for design at low to moderate inversion level in an advanced technology for which simulation-based studies are often used by designer as early sizing stage. The designed LNA consumes 0.57 mW and achieves an 18.4 dB gain with 3.3 dB of NF.

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Dates et versions

hal-03640029 , version 1 (29-07-2022)

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Paternité - Pas d'utilisation commerciale

Identifiants

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Sylvain Bourdel, Serge Subias, Mohamed Khalil Bouchoucha, Manuel J. Barragan, Andreia Cathelin, et al.. A gm/ID Design Methodology for 28 nm FD-SOI CMOS Resistive Feedback LNAs. 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2021), Nov 2021, Dubaï, United Arab Emirates. pp.1-4, ⟨10.1109/ICECS53924.2021.9665492⟩. ⟨hal-03640029⟩
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