%0 Conference Proceedings %T Extraction of small signal equivalent circuit for de-embedding of 3D vertical nanowire transistor %+ Laboratoire de l'intégration, du matériau au système (IMS) %+ NaMLab gGmbH %+ Centre National de la Recherche Scientifique (CNRS) %+ Équipe Matériaux et Procédés pour la Nanoélectronique (LAAS-MPN) %A Neckel Wesling, Bruno %A Deng, Marina %A Chhandak, Mukherjee %A Kumar, Abhishek %A Larrieu, Guilhem %A Trommer, Jens %A Mikolajick, Thomas %A Maneux, Cristell %< avec comité de lecture %Z Rapport LAAS n° 22416 %( Proceedings EuroSOI-ULIS 2022 %B 8th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS 2022) %C Udine, Italy %P à paraître %8 2022-05-18 %D 2022 %K test structure %K equivalent circuit %K parasitic components %K RF measurements %K de-embedding %Z Engineering Sciences [physics]/Micro and nanotechnologies/MicroelectronicsConference papers %X In this paper, we present an improved methodology to extract the small signal electrical equivalent circuit of the parasitic elements using RF test-structures for a 3D vertical nanowire transistor technology. The methodology is based on the extraction of parasitic elements from a virtual open structure constructed using electromagnatic simulation and calibrated against on-wafer S-parameter measurements up to 40 GHz. The electrical equivalent circuit of the passive device was then used for deembedding of the transistor S-parameters for extraction of intrinsic small signal parameters such as the gate capacitances. %G English %2 https://hal.science/hal-03864048/document %2 https://hal.science/hal-03864048/file/EUROSOI_ULIS_BNW06.pdf %L hal-03864048 %U https://hal.science/hal-03864048 %~ UNIV-TLSE2 %~ UNIV-TLSE3 %~ CNRS %~ INSA-TOULOUSE %~ LAAS %~ IMS-BORDEAUX %~ OPENAIRE %~ IMS-BORDEAUX-FUSION %~ LAAS-MPN %~ LAAS-MICRO-NANO-BIO-TECHNOLOGIES %~ INSA-GROUPE %~ TOULOUSE-INP %~ UNIV-UT3 %~ UT3-INP %~ UT3-TOULOUSEINP