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authFullName_s : Arnaud Poittevin

Why neuromorphic computing need novel 3D technologies? A view from FVLLMONTI European project consortium (Invited)

Cristell Maneux , Mukherjee Chhandak , Marina Deng , Maeva Dubourg , Lucas Réveil et al.
High Performance Embedded Architecture and Compilation, Computing Systems Week, (HiPEAC CSW) Autumn 2021, Oct 2021, Lyon, France
Conference papers hal-03408071v1
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Circuit Design Flow dedicated to 3D vertical nanowire FET

Cristell Maneux , Mukherjee Chhandak , Marina Deng , Bruno Neckel Wesling , Lucas Réveil et al.
IEEE Latin American Electron Devices Conference (LAEDC 2022), Jul 2022, Puebla, Mexico. ⟨10.1109/LAEDC54796.2022.9908233⟩
Conference papers hal-03765071v1
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Circuits logiques avec transistors basés sur des nanofils verticaux : Défis et opportunités en termes de conception physique et logique

Arnaud Poittevin
Autre. Université de Lyon, 2022. Français. ⟨NNT : 2022LYSEC024⟩
Theses tel-03981254v1
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3D logic cells design and results based on Vertical NWFET technology including tied compact model

Mukherjee Chhandak , Marina Deng , François Marc , Cristell Maneux , Arnaud Poittevin et al.
28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC) 2020, Oct 2020, Salt Lake City (virtual), United States. ⟨10.1109/VLSI-SOC46417.2020.9344094⟩
Conference papers hal-03166674v1
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Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors

Lucas Réveil , Mukherjee Chhandak , Cristell Maneux , Marina Deng , François Marc et al.
30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2022), Oct 2022, Patras, Greece. 2 p., ⟨10.1109/VLSI-SoC54400.2022.9939576⟩
Conference papers hal-03765079v1
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Emerging Technologies: Challenges and Opportunities for Logic Synthesis

Alberto Bosio , Mayeul Cantan , Cédric Marchand , Ian O'Connor , Petr Fiser et al.
2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2021, Vienna (virtual), Austria. pp.93-98, ⟨10.1109/DDECS52668.2021.9417062⟩
Conference papers hal-03266914v1
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Compact Modeling of 3D Vertical Junctionless Gate-allaround Silicon Nanowire Transistors Towards 3D Logic Design

Mukherjee Chhandak , Arnaud Poittevin , Ian O'Connor , Guilhem Larrieu , Cristell Maneux et al.
Solid-State Electronics, 2021, 183, pp.108125. ⟨10.1016/j.sse.2021.108125⟩
Journal articles hal-03429568v1
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A Logic Cell Design and routing Methodology Specific to VNWFET

Arnaud Poittevin , Ian O'Connor , Cédric Marchand , Alberto Bosio , Cristell Maneux et al.
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS), Jun 2022, Quebec City, Canada. pp.460-464, ⟨10.1109/NEWCAS52662.2022.9842100⟩
Conference papers hal-03864493v1

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model

Arnaud Poittevin , Chhandak Mukherjee , Ian O'Connor , Cristell Maneux , Guilhem Larrieu et al.
VLSI-SoC: Design Trends, 621, Springer International Publishing, pp.301-321, 2021, IFIP Advances in Information and Communication Technology, ⟨10.1007/978-3-030-81641-4_14⟩
Book sections hal-03371673v1
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Analysis of Energy-Delay-Product of a 3D Vertical Nanowire FET Technology

Ian O'Connor , Arnaud Poittevin , Sébastien Le Beux , Alberto Bosio , Zlatan Stanojevic et al.
EuroSOI-ULIS, Sep 2021, Caen, France. ⟨10.1109/EuroSOI-ULIS53016.2021.9560180⟩
Conference papers hal-03407210v1
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Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence (Invited)

Cristell Maneux , Mukherjee Chhandak , Marina Deng , Maeva Dubourg , Lucas Réveil et al.
67th Annual IEEE International Electron Devices Meeting (IEDM 2021), Dec 2021, San Fransisco, United States. ⟨10.1109/IEDM19574.2021.9720572⟩
Conference papers hal-03408078v1