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Communication Dans Un Congrès Année : 2023

Experimental Demonstration of Memristor Delay-Based Logic In-Memory Ternary Neural Network

Résumé

We present a fabricated hybrid CMOS/memristor integrated circuit for efficient implementation of Ternary Neural Networks. Our approach overcomes memristor resolution limitations and uses a simple sense amplifier that simultaneously reads memristor states and performs the TNN multiplication operations. The test chip validates our scheme, paving the way for energy-efficient, nanosecond-latency TNNs.
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Dates et versions

hal-04270396 , version 1 (04-11-2023)

Identifiants

Citer

A. Renaudineau, K.-E. Harabi, C. Turck, A. Laborieux, E. Vianello, et al.. Experimental Demonstration of Memristor Delay-Based Logic In-Memory Ternary Neural Network. 2023 Silicon Nanoelectronics Workshop (SNW), Jun 2023, Kyoto, Japan. pp.43-44, ⟨10.23919/SNW57900.2023.10183957⟩. ⟨hal-04270396⟩
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