Experimental Demonstration of Memristor Delay-Based Logic In-Memory Ternary Neural Network
Abstract
We present a fabricated hybrid CMOS/memristor integrated circuit for efficient implementation of Ternary Neural Networks. Our approach overcomes memristor resolution limitations and uses a simple sense amplifier that simultaneously reads memristor states and performs the TNN multiplication operations. The test chip validates our scheme, paving the way for energy-efficient, nanosecond-latency TNNs.
Domains
Engineering Sciences [physics]| Origin | Files produced by the author(s) |
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