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Article Dans Une Revue IEEE Transactions on Electron Devices Année : 2017

Assessment of the Electrical Performance of Short Channel InAs and Strained Si Nanowire FETs

Résumé

We present a numerical study aimed to benchmark short gate InAs nanowire-FETs (NW-FETs) against their strained Si (sSi) counterpart. Our full-quantum simulations focus on both gate-length scaling and device variability and include the impact of electron-phonon scattering and surface roughness (SR). Interestingly, we found that SR improves the subthreshold-voltage swing (SS) of short gate-length InAs devices by inducing a reduced source-to-drain tunneling. Hence, InAs NW-FETs exhibit a larger immunity to the roughness-induced degradation of the ON-current, whereas they suffer froma larger OFF-current and SS variability with respect to the sSi ones. According to our results, InAs NW-FETs could compete with sSi NW-FETs only for very short gate lengths, when the device performance is significantly degraded, while for longer devices sSi NW-FETs remain a more effective and reliable choice due to the higher gate overdrive charge.
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Dates et versions

hal-01694193 , version 1 (26-01-2018)

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Corentin Grillet, Demetrio Logoteta, Alessandro Cresti, Marco G. Pala. Assessment of the Electrical Performance of Short Channel InAs and Strained Si Nanowire FETs. IEEE Transactions on Electron Devices, 2017, 64 (5), pp.2425-2431. ⟨10.1109/TED.2017.2679226⟩. ⟨hal-01694193⟩
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